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SL2101 Synthesized Broadband Converter with Programmable Power
Data Sheet Features
* * Single chip synthesized broadband solution Configurable as both up converter and downconverter requirements in double conversion tuner applications Incorporates 8 programmable mixer power settings Compatible with digital and analogue system requirements CSO -65 dBc, CTB -68 dBc (typical) Extremely low phase noise balanced local oscillator, with very low fundamental and harmonic radiation PLL frequency synthesizer designed for high comparison frequencies and low phase noise Buffered crystal output for pipelining system reference frequency I2C Controlled Ordering Information SL2101C/KG/NP1P SL2101C/KG/NP1Q SL2101C/KG/NP2P SL2101C/KG/NP2Q SL2101C/KG/LH2N SL2101C/KG/LH2Q SSOP SSOP SSOP* SSOP* MLP* MLP* Tubes Tape & Reel Tubes Tape & Reel Trays Tape& Reel
August 2004
* * * *
* Pb free All codes baked and drypacked -40C to +85C
* * *
Description
The SL2101 is a fully integrated single chip broadband mixer oscillator with low phase noise PLL frequency synthesizer. It is intended for use in double conversion tuners as both the up and down converter and is compatible with HIIF frequencies up to 1.4 GHz and all standard tuner IF output frequencies. It also contains a programmable power facility for use in systems where power consumption is important. The device contains all elements necessary, with the exception of local oscillator tuning network, loop filter and crystal reference to produce a complete synthesized block converter, compatible with digital and analogue requirements.
Applications
* * * * * Double conversion tuners Digital Terrestrial tuners Cable telephony Cable Modems MATV
Figure 1 - Functional Block Diagram 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002 - 2004, Zarlink Semiconductor Inc. All Rights Reserved.
SL2101
Data Sheet
XTAL CAP XTAL SDA SCL BUFREF Vccd Vee Vee RF RFB Vee VccRF Vee IFOUTPUTB
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
PUMP DRIVE PORT P0 Vee ADD Vee VccLO LOB LO VccLO Vee VccLO Vee IFOUTPUT NP 28
Figure 2 - Pin Diagram SSOP Package
XTAL CAP
Vccd nc nc RF RFB nc VccRF
1 2 3 4
28 27 26 25 24 23 22 21 Pin 1 Ident 20 19 18 17 16 8 nc 9 nc 15 10 11 12 13 14 IFOUTPUTB IFOUT nc nc VccLO
PORT P0
DRIVE
PUMP
SDA
XTAL
SCL
ADD nc VccLO LOB LO VccLO nc
5 6 7
Vee to pad under package
Figure 3 - Pin Diagram MLP Package
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Zarlink Semiconductor Inc.
SL2101
Quick Reference Data
All data applies at maximum power setting with the following conditions unless otherwise stated; a) nominal loads as follows; 1220 MHz output load as in Figure 4 44 MHz output load as in Figure 5 b) input signal per carrier of 63 dBV Characteristic RF input operating range Input noise figure, SSB, 50-860 MHz 860-1400 Conversion gain CTB (fully loaded matrix) CSO (fully loaded matrix) P1 dB input referred Local oscillator phase noise as upconverter SSB @ 10 kHz offset SSB @ 100 kHz offset Local oscillator phase noise as downconverter SSB @ 10 kHz offset SSB @ 100 kHz offset Local oscillator phase noise floor PLL spurs on converted output with input @ 60 dBV PLL maximum comparison frequency PLL phase noise at phase detector
*dBm assumes a 75 characteristic impedance, and 0 dBm = 109 dBV
Data Sheet
Units 50-1400 6.5 - 8.5 8.5 - 12 12 -68 -65 110 -90 -112 -93 -115 -136 <-70 4 -152 MHz dB dB dB dBc dBc dBV dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc MHz dBc/Hz
Functional Description
The SL2101 is a broadband wide dynamic range mixer oscillator with on-board I2C bus controlled PLL frequency synthesizer, optimized for application in double conversion tuner systems as both the up and down converter. It also has application in any system where a wide dynamic range broadband synthesized frequency converter is required. The SL2101 is a single chip solution containing all necessary active circuitry and simply requires an external tuneable resonant network for the local oscillator sustaining network. The pin assignment is contained in Figures 2 and 3 for the SSOP and MLP packages and the block diagram in Figure 1. The device also contains a programmable facility to adjust the power in the lna/mixer so allowing power to be traded against intermodulation performance for power critical applications, such as telephony modems.
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SL2101
Converter Section
Data Sheet
In normal application the RF input is interfaced through appropriate impedance matching and an AGC front end to the device input. The RF input preamplifier of the device is designed for low noise figure, within the operating region of 50 to 1400 MHz and for high intermodulation distortion intercept so offering good signal to noise plus composite distortion spurious performance when loaded with a multi carrier system. The preamplifier also provides gain to the mixer section and back isolation from the local oscillator section. The lna/mixer current and hence signal handling and device power consumption are programmable through the I2C bus as tabulated in Figure 7. The typical RF input impedance and matching network for broadband upconversion are contained in Figures 8 and 9 respectively and for narrow band downconversion in Figures 10 and 11 respectively. The input referred two tone intermodulation test condition spectrum at maximum power setting is shown in Figure 12. The typical input NF and gain versus frequency and NF specification limits, over selectable power settings are contained in Figures 13, 14 and 15 respectively. The output of the preamplifier is fed to the mixer section which is optimized for low radiation application. In this stage the RF signal is mixed with the local oscillator frequency, which is generated by the on-board oscillator. The oscillator block uses an external tuneable network and is optimized for low phase noise. The typical oscillator application as an upconverter is shown in Figure 16 and the typical phase noise performance in Figure 17. The typical oscillator application as a downconverter is shown in Figure 18, and the phase noise performance in Figure 19. This oscillator block interfaces direct with the internal PLL to allow for frequency synthesis of the local oscillator. Finally the output of the mixer provides an open collector differential output drive. The device allows for selection of an IF in the range 30-1400 MHz so covering standard HIIFs between 1 and 1.4 GHz and all conventional tuner output IFs. When used as a broadband upconverter to a HIIF the output should be differentially loaded, for example with a differential SAW filter, to maximize intermodulation performance. A nominal load in maximum power setting is shown in Figure 4, which will typically be terminated with a differential 200 load. When used as a narrowband downconverter the output should be differentially loaded with a discrete differential to single ended converter as in Figure 5, shown tuned to 44 MHz IF. Alternatively loading can be direct into a differential input amplifier or SAWF, in which case external loads to Vcc will be required. An example load for 44 MHz application with a gain of 16 dB is contained in Figure 6. The NF and gain with recommended load versus power setting are contained in Figure 20. The typical IF output impedance as upconverter and downconverter are contained in Figures 21 and 22 respectively. In all applications care should be taken to achieve symmetric balance to the IF outputs to maximize intermodulation performance. The typical key performance data at 5V Vcc and 25 deg C ambient are shown in the section 'Quick Reference Data'. PLL Frequency Synthesizer The PLL frequency synthesizer section contains all the elements necessary, with the exception of a reference frequency source and loop filter to control the oscillator, so forming a complete PLL frequency synthesized source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. The LO signal from the oscillator drives an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier interfaces direct with the 15-bit fully programmable divider. The programmable divider is of MN+A architecture, where the dual modulus prescaler is 16/17, the A counter is 4-bits, and the M counter is 11 bits. The output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. This frequency is derived either from the on-board crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to
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Zarlink Semiconductor Inc.
SL2101
Data Sheet
the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as detailed in figure 23. Typical applications for the crystal oscillator are contained in Figure 24 and Figure 25. Figure 25 is used when driving a second SL2101 as a downconverter. The output of the phase detector feeds a charge pump and loop amplifier, which when used with an external loop filter and high voltage transistor, integrates the current pulses into the varactor line voltage, used for controlling the oscillator. The programmable divider output Fpd divided by two and the reference divider output Fcomp can be switched to port P0 by programming the device into test mode. The test modes are described in Figure 26. The crystal reference frequency can be switched to BUFREF output by bit RE as described in Figure 27. The BUFREF output is not available on the MLP package.
Programming
The SL2101 is controlled by an I2C data bus and is compatible with both standard and fast mode formats. Data and Clock are fed in on the SDA and SCL lines respectively as defined by I2C bus format. The device can either accept data (write mode), or send data (read mode). The LSB of the address byte (R/W) sets the device into write mode if it is low, and read mode if it is high. Tables 1 and 2 in Figure 28 illustrate the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one device in an I2C bus system. Figure 28, Table 3 shows how the address is selected by applying a voltage to the 'ADD' input. When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period, and during following acknowledge periods after further data bytes are received. When the device is programmed into read mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an internal STOP condition, which inhibits further reading. Write Mode With reference to Figure 28, Table 1, bytes 2 and 3 contain frequency information bits 214 -20 inclusive. Byte 4 controls the synthesizer reference divider ratio, see Figure 23 and the charge pump setting, see Figure 29. Byte 5 controls the test modes, see Figure 26, the buffered crystal reference output select RE, see Figure 27, the power setting, see Figure 7 and the output port P0. After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines whether the byte is interpreted as a byte 2 or 4, a logic '0' indicating byte 2, and a logic '1' indicating byte 4. Having interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively. Having received two complete data bytes, additional data bytes can be entered, where byte interpretation follows the same procedure, without re-addressing the device. This procedure continues until a STOP condition is received. The STOP condition can be generated after any data byte, if however it occurs during a byte transmission, the previous byte data is retained. To facilitate smooth fine tuning, the frequency data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the generation of a STOP condition. Read Mode When the device is in read mode, the status byte read from the device takes the form shown in Figure 28, Table 2. Bit 1 (POR) is the power-on reset indicator, and this is set to a logic '1' if the Vcc supply to the device has dropped below 3V (at 25 C), e.g., when the device is initially turned ON. The POR is reset to '0' when the read sequence is terminated by a STOP command. When POR is set high this indicates that the programmed information may have been corrupted and the device reset to the power up condition. Bit 2 (FL) indicates whether the synthesizer is phase locked, a logic '1' is present if the device is locked, and a logic '0' if the device is unlocked.
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Programmable Features Synthesizer programmable divider Reference programmable divider Charge pump current Power setting Function as described above Function as described above.
Data Sheet
The charge pump current can be programmed by bits C1 & C0 within data byte 4, as defined in Figure 29. The device power and hence signal handling can be programmed by bits I2 - I0 within data byte 5, as defined in Figure 7. In all power settings the synthesizer remains enabled to facilitate rapid PLL lock reacquisition
Test mode General purpose ports, P0
The test modes are defined by bits T2 - T0 as described in Figure 26. The general purpose port can be programmed by bits P0; Logic '1' = on Logic '0' = off (high impedance) - this is the default state at device power on
Buffered crystal reference output, BUFREFThe buffered crystal reference frequency can be switched to the BUFREF output by bit RE as described in Figure 27. The BUFREF output defaults to the 'ON' condition at device power up. This output is only available on the SSOP package.
33 15
OUTPUT
Vcc
200 10nH
SL2101
10nH 200 14 33
SAWF
OUTPUTB
Figure 4 - Nominal Output Load as Upconverter into Differential SAWF
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Zarlink Semiconductor Inc.
SL2101
Vcc 15 pF
Data Sheet
15
820 nH
OUTPUT SL2101
14 820 nH 10 uH 10 nF 15 pF
Figure 5 - Nominal Output Load as Downconverter, 44 MHz IF
10 nF
OUTPUT
15
Vcc
680 nH
SL2101
14
100 nF
680 nH 10 nF
OUTPUTB
Figure 6 - Output Load as Downconverter to a Differential Amplifier
I2
I1
I0
Supply Current in mA Typ. Max.
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
90* 67 56 51 82 59 48 43
Figure 7 - Supply Current
120 89 75 68 109 78 64 57
* default setting on SL2101
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Zarlink Semiconductor Inc.
SL2101
27 Jul 2001 11:24:54 -99.426 1.6007 pF 1 000.000 000 MHz
Data Sheet
CH1
S 11 DB1
1 U FS 4.7V
1_: 4.3164
PRm Cor Avg 16 Smo
Z0 50
2_: 3.7266 -80.117 1.15 GHz 3_: 4.1328 -70.223 1.25 GHz 4_: 4.7617 -58.166 1.4 GHz
1
START 1 000.000 000 MHz
4
2 3 STOP 1 400.000 000 MHz
Figure 8 - Typical RF Input Impedance as Broadband Upconverter (Maximum Power Setting)
100nF 75 RFIN
9 RFINPUT 10
200 100nF 47nH
RFINPUTB
SL2101
Figure 9 - RF Input Impedance Matching Network as 50 - 860 MHz Upconverter
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Zarlink Semiconductor Inc.
SL2101
CH1 S 11 UA6 PRm Cor Avg 16 Smo 1 U FS 4.7V 1_: 20.07 27 Jul 2001 09:05:31 -46.965 3.3888 pF 1 000.000 000 MHz
Data Sheet
Z0 75
2_: 19.795 -34.527 1.15 GHz 3_: 20.666 -26.233 1.25 GHz 4_: 25.772 -15.155 1.4 GHz
4
3 2
1
START 1 000.000 000 MHz
STOP 1 400.000 000 MHz
Figure 10 - Typical RF Input Impedance as Narrow Band Downconverter (maximum power setting)
2.7pF RFIN
9
RFINPUT
10 200 3.9nH 10nF RFINPUTB
SL2101
Figure 11 - RF Input Impedance Matching Network as 1.22 GHz Downconverter
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Zarlink Semiconductor Inc.
SL2101
Data Sheet
94 dBuV
IIM3 -46dBc
IIM2-47dBc
48 dBuV 47 dBuV
df f2-f1 f1-df f1 f2 f2+df
Figure 12 - Two Tone Intermodulation Test Condition Spectrum, Input Referred
8
7
6
Noise Figure (dB)
5
4
3
2
1
0
0
100
200
300
400
500
600
700
800
900
Input frequency (MHz)
Figure 13 - Input NF, Typical (Maximum Power Setting)
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Zarlink Semiconductor Inc.
SL2101
11 10 9 Conversion gain(in dB) 8 7 6 5 4 3 2 1 0 0 100 200 300 400 500 600 700 800 900 Input frequency(in MHz)
Data Sheet
Gain
Figure 14 - Conversion Gain as Upconverter (Maximum Power Setting)
I2
I1
I0
Typ NF (dB)
Gain (dB)
typ CSO* (dBc)
typ CTB* (dBc)
typ IPIP2 (dBV)
typ IPIP3 (dBV)
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
6.8 6.0 5.8 6.5 8.7 6.2 5.9 6.4
10.1 9.1 7.6 5.4 10.4 10.0 8.3 5.8
-65 -60 -56 -49 -63 -64 -58 -50
-65 -54 -42 -35 -60 -56 -42 -34
144 141 132 129 146 142 133 126
121 114 108 106 117 113 106 103
Figure 15 - Upconverter Gain, NF and Intermodulation with Recommended Load Versus Power Setting
* Measured with 128 channels at +7 dBmV.
BB555
1 k
2 pF
Varactor line
3x0.5 mm
3x1.5 mm
BB555 3x2.75 mm
(centre)
Figure 16 - Upconverter Oscillator Application
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Zarlink Semiconductor Inc.
SL2101
-85
Data Sheet
Phase noi se(in dBc/Hz)
-87 -89
-91
PN
-93
-95
0
100
200
300
400
500
600
700
800
900
Figure 17 - Oscillator Typical Phase Noise Performance at 10 kHz Offset
2.5 pF
20 4.3 nH 21
1 k
Varactor line
BB555
Figure 18 - Downconverter Oscillator Application
100 98 96 Phase noise (at 10 kHz offset) 94 92 90 88 86 84 82 80 1040 1060 1080 1100 1120 1140 1160 1180 1200 2201
LO frequency
Figure 19 - Typical Phase Noise Performance as Downconverter at 10 kHz Offset
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Zarlink Semiconductor Inc.
SL2101
Typ NF (dB) typ IPIP3 (dBV)
Data Sheet
I2
I1
I0
Gain (dB)
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
10.3 9.3 8.8 8.7 11.6 9.0 8.3 8.0
15.6 15.1 14.0 12.1 15.4 15.1 13.9 11.9
124 119 112 106 121.3 119.7 112.6 106.3
Figure 20 - Downconverter Gain, NF and IP3 with Recommended (Fig. 4) Load Versus Power Setting
CH1 S 11 DB1 PRm Cor Avg 16 Smo 1 U FS 4.7V 1_: 4.3164 27 Jul 2001 11:24:54 -99.426 1.6007 pF 1 000.000 000 MHz
Z0 50
2_: 3.7266 -80.117 1.15 GHz 3_: 4.1328 -70.223 1.25 GHz 4_: 4.7617 -58.166 1.4 GHz
1
START 1 000.000 000 MHz
4
2 3 STOP 1 400.000 000 MHz
Figure 21 - Typical IF Output Impedance as Upconverter, Single-Ended
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Zarlink Semiconductor Inc.
SL2101
27 Jul 2001 09:48:39 -1.1071 k 7.1882 pF 20.000 000 MHz
Data Sheet
CH1
S 11 UA6
1 U FS 4.7V
1_: 1.3588 k
PRm Cor Avg 16 Smo
Z0 50
2_: 606.87 -695.97 40 MHz 3_: 305.72 -549.5 70 MHz 4_: 213.55 -449.58 100 MHz
1
2 3 4
START 10.000 000 MHz
STOP 100.000 000 MHz
Figure 22 - Typical IF Output Impedance as Downconverter, Single-Ended R4 R3 R2 R1 R0 Ratio
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
2 4 8 16 32 64 128 256 Illegal state 5 10 20 40 80 160 320
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Zarlink Semiconductor Inc.
SL2101
R4 R3 R2 R1 R0 Ratio
Data Sheet
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Illegal state 6 12 24 48 96 192 384 Illegal state 7 14 28 56 112 224 448
Figure 23 - Reference Division Ratios
1 47pf 47pf 2 4MHz
XTALCAP
XTAL
Figure 24 - Standard Application
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Zarlink Semiconductor Inc.
SL2101
Data Sheet
1 XTALCAP 47pF 2 47pF 4MHz SL2101 DOWNCONVE RTER XTAL 1 XTALCAP 820nH 10pF 10k SL2101 2 UPCONVE RTER XTAL
Figure 25 - Application When Driving Two SL2101 from One Crystal T2 T1 T0 Test Mode Description
0 0 0 0 1 1
0 0 1 1 0 0
0 1 0 1 0 1
Normal operation Charge pump sink * Status byte FL set to logic `0' Charge pump source * Status byte FL set to logic `0' Charge pump disabled * Status byte FL set to logic `1' Normal operation and Port P0 = Fpd/2 Charge pump sink * Status byte FL set to logic `0' Port P0 = Fcomp Charge pump source * Status byte FL set to logic `0' Port P0 = Fcomp Charge pump disabled * Status byte FL set to logic `1' Port P0 = Fcomp
Figure 26 - Test Modes
1
1
0
1
1
1
* clocks need to be present on crystal and local oscillator to enable charge pump test modes and to toggle status byte bit FL.
RE
BUFREF output
0 1
disabled, high impedance enabled
Note:The BUFREF output is only available on the SSOP package
Figure 27 - Buffered Crystal Reference Output Select
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Zarlink Semiconductor Inc.
SL2101
Data Sheet
MSB Address Programmable divider Programmable divider Control data Control data
LSB
1 0
1 214 26 C1 T1
0 213 25 C0 T0
0 212 24 R4 I2
0 211 23 R3 I1
MA1 210 22 R2 I0
MA0 29 21 R1 RE
0 28 20 R0 P0
A A
Byte 1 Byte 2
27 1 T2
A
Byte 3
A A
Byte 4 Byte 5
Table 1 - Write Data Format (MSB is transmitted first)
MSB Address Programmable divider LSB
1 POR
1 FL
0 0
0 0
0 0
MA1 0
MA0 0
1 0
A A
Byte 1 Byte 2
Table 2 - Read Data Format (MSB is transmitted first)
A MA1,MA0 214-20 I2-I0 C1-C0 R4-R0 T2-T0 RE P0 POR FL : : : : : : : : : : : Acknowledge bit Variable address bits (see Table 3) Programmable division ratio control bits lna/mixer power select (see Figure 7) Charge pump current select (see Figure 29) Reference division ratio select (see Figure 23) Test mode control bits (see Figure 26) Buffered crystal reference output enable (see Figure 27 P0 port output state Power on reset indicator Phase lock flag
MA1
MA0
Address input voltage level
0 0 1 1
0 1 0 1
0-0.1Vcc Open circuit 0.4Vcc - 0.6 Vcc # 0.9 Vcc - Vcc
Table 3 - Address Selection Figure 28 - Read/Write Data Formats
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Zarlink Semiconductor Inc.
SL2101
Current in mA C1 C0 Min. Typ. Max.
Data Sheet
0 0 1 1
0 1 0 1
+-98 +-210 +-450 +-975
+-130 +-280 +-600 +-1300
+-162 +-350 +-750 +-1625
Figure 29 - Charge Pump Current Electrical Characteristics - Test conditions (unless otherwise stated). Tamb = -40o to 85oC, Vee= 0V, Vcc=5 V+-5%. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage at maximum power setting unless otherwise stated. Characteristic Pin Min. Typ. Max. Units Conditions
Supply current
6, 12,17, 19, 22
90
120
mA
IF outputs will be connected to Vcc through the differential load as in Figures 4, 5 & 6. See Figure 7 for programmable settings. Operating condition only. Operating condition only. Operating condition only. Within channel bandwidth of 8 MHz and with input power of 60 dBV.
Input frequency range Output frequency range Composite peak input signal All synthesizer related spurs on IF Output
Upconverter application
9, 10 14, 15 9, 10 14, 15
50 30 97
1400 1400
MHz MHz dBV
-60
dBc
Input frequency range Input impedance Input return loss Input Noise Figure
9, 10
50 75 6
860
MHz
See Figure 8. With input matching network as in Figure 9. Tamb=27C, see Figure 13, with input matching network as in Figure 9. See Figure 15 for programmable settings. Differential voltage gain to 200 load on output of SAWF as in Figure 4, see Figure 14. See Figure 15 for programmable settings.
dB 9.5 dB
Conversion gain
9
dB
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Zarlink Semiconductor Inc.
SL2101
Characteristic Pin Min. Typ. Max. Units
Data Sheet
Conditions
Gain variation across operation range Gain variation within channel Through gain CSO
-1
+1 0.5 -20 -65
dB dB dB dBc
50-860 MHz Channel bandwidth 8 MHz within operating frequency range. 45-1400 MHz Measured with 128 channels at 62 dBV. See Figure 15 for programmable settings. Measured with 128 channels at 62 dBV. See Figure 15 for programmable settings. See Note 2. See Figure 15 for programmable settings. See Note 2. See Figure 15 for programmable settings. See Note 2. See Figure 12. See Note 2. See Figure 12. Maximum tuning range 0.9 GHz determined by application. Application as in Figure 16. See Figure 17.
CTB
-68
dBc
IPIP22T
141
dBuV
IPIP32T
117
dBuV
IPIM22T IPIM32T LO operating range LO phase noise, SSB @ 10 kHz offset @ 100 kHz offset LO phase noise floor IF output frequency range IF output impedance
Downconverter application
-47 -46 1 2.3
dBc dBc GHz
-86 -106 -136 14, 15 1 1.4
dBc/Hz dBc/Hz dBc/Hz GHz
Application as in Figure 16.
See Figure 21.
Input frequency range Input impedance Input return loss Input Noise Figure
9, 10
1000 75 12
1400
MHz
See Figure 10. With input matching network as in Figure 11. Tamb=27C, with input matching network as in Figure 11. See Figure 20 for programmable settings.
dB 14 dB
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Zarlink Semiconductor Inc.
SL2101
Characteristic Pin Min. Typ. Max. Units
Data Sheet
Conditions
Conversion gain
12
dB
Differential voltage gain to 50 load on output of impedance transformer as in Figure 6. See Figure 20 for programmable settings. Channel bandwidth 8 MHz within operating frequency range. 45-1400 MHz See Note 2. See Note 2. See Figure 12. Maximum tuning range determined by application, see Note 4. Application as in Figure 18. See Figure 19.
Gain variation within channel Through gain IPIP32T IPIM32T LO operating range 1 117
0.5 -20
dB dB dBV
-46 2.3
dBc GHz
LO phase noise, SSB @ 10 kHz offset @ 100 kHz offset LO phase noise floor IF output frequency range IF output impedance
Synthesizer
-92 -112 -136 14, 15 100
dBc/Hz dBc/Hz dBc/Hz MHz
Application as in Figure 18.
See Figure 22.
SDA, SCL Input high voltage Input low voltage Input high current Input low current Leakage current Hysterysis SDA output voltage SCL clock rate Charge pump output current Charge pump output leakage
3, 4 3 0 5.5 1.5 10 -10 10 0.4 3 4 28 28 +-3 +-10 nA 0.4 0.6 400 V V kHz See Figure 29. Vpin = 2 V Vpin = 2 V Isink = 3 mA Isink = 6 mA V V
A A A
I2C `Fast mode' compliant
Input voltage = Vcc Input voltage = Vee Vcc=Vee
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Zarlink Semiconductor Inc.
SL2101
Characteristic Pin Min. Typ. Max. Units
Data Sheet
Conditions
Charge pump drive output current Crystal frequency Recommended crystal series resistance External reference input frequency External reference drive level Phase detector comparison frequency Equivalent phase noise at phase detector
27 1,2
0.5 2 10 20 200 20 0.5 4
mA MHz
Vpin = 0.7 V See Figure24 and Figure 25 for application. 4 MHz parallel resonant crystal Sinewave coupled through 10 nF blocking capacitor Compatible with BUFREF output. (SSOP package only)
2 2
2 0.2
MHz Vpp MHz
SSB, within loop bandwidth -148 -152 -158 dBc/Hz dBc/Hz dBc/Hz 32767 Fcomp = 1 MHz Fcomp = 250 kHz Fcomp = 62.5 kHz
Local oscillator programmable divider division ratio Reference division ratio Output port sink current leakage current BUFREF output output amplitude output impedance Address select Input high current Input low current
Note 1: Note 2: Note 3: Note 4: Note 5:
240
See Figure 23. 26 2 10 5 0.35 250 Vpp
mA A
See Note 3. Vport = 0.7 V Vport =Vcc AC coupled. Note 5. Enabled by bit RE=1 and default state on power-up. BUFREF output only available on SSOP package See Figure 28, Table 3 Vin=Vcc Vin=Vee
1 -0.5
mA mA
All power levels are referred to 75 and 0 dBm = 109 dBV Any two tones within RF operating range at 94 dBV beating within band, with output load as in Figure 4 Port powers up in high impedance state To maximise phase noise the tuning range should be minimised and Q of resonator maximised. The application as in Figure 18 has a tuning range of 200 MHz. If the BUFREF output is not used it should be left open circuit or connected to Vccd and disabled by setting RE = '0'.
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Zarlink Semiconductor Inc.
SL2101
Absolute Maximum Ratings - All voltages are referred to Vee at 0 V (pins 7, 8, 11, 13, 16, 18, 23, 25). Characteristic Pin Min. Max. Units Conditions
Data Sheet
Supply voltage, Vcc
6, 12, 17, 19, 22 9, 10
-0.3
6
V
RF input voltage All I/O port DC offsets SDA, SCL DC offsets Storage temperature Junction temperature Package thermal resistance, chip to case (SSOP) Package thermal resistance, chip to ambient (SSOP) Power consumption at 5.25 V ESD protection (pins 3-28) ESD protections (pins 1, 2)
117 -0.3 Vcc+0.3 6 150 125 20 85 630 1 0.75
dBuV V V
C C
Differential, AC coupled inputs
3, 4
-0.3 -55
Vcc = Vee to 5.25 V
Power applied.
C/W
C/W
mW kV kV
Maximum power setting. Mil-std 883B method 3015 cat1
22
Zarlink Semiconductor Inc.
SL2101
Data Sheet
RF inputs
Oscillator inputs
IF outputs
Figure 30 - Input and Output Interface Circuits (RF section)
23
Zarlink Semiconductor Inc.
SL2101
Data Sheet
Vccd
1
200A
Reference oscillator
Loop amplifier
Vccd
120K
*
* On SDA only SDA/SCL (pins 3 and 4) ADD input
Vccd P0
1mA
Output port
BUFREF output
Figure 31 - Input and Output Interface Circuits (PLL section)
24
Zarlink Semiconductor Inc.
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